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| 1 ax84110 l asix electronics corp preliminary usb2.0 to local cpu bus controller document no.: ax84110 / v0.0 / dec. 16 ?02 features: n compliant with usb specification 1.0, 1.1 and 2.0 n support both 8 bit and 16 bit local cpu interfaces include mcs - 51 series, 80186 series, mc68k series cpu, isa bus and pcmcia bus n capability full/high speed usb device with bus power n support 4 endpoints on usb and 4 general purpose in/out pins n embedded 2k*16 bit sram n 128 - pin lqfp low profile package n support suspended mode and remote wakeup n single 12mhz clock input, pure 3 .3v operation with 5v i/o tolerance n support (93c56/93c66) 256/512 bytes serial eeprom (used for saving usb descriptors) n support 4 set of status change reply n support automatic loading of application device, from application device usb descriptors and adapt er configuration from eeprom when power - on initialization product description the ax84110 usb2.0 to local cpu bus controller is a high performance and with embedded 2k*16 sram and compliant with usb standard v1.0, v1.1 and v2.0. the ax84110 supports full /high speed usb device with bus power capability and supports both 8 bit and 16 bit local cpu interfaces include mcs - 51 series, 80186 series, mc68k series cpu and isa bus and pcmcia bus. ax84110 eeprom compliant with cpu bus application device as 8051,80186,68k,isa,pcmcia usb bus
2 ax84110 l asix electronics corp preliminary always contact asix for possible updates before starting a design. this data sheet contains new products information. asix electronics reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. 3 ax84110 l asix electronics corp preliminary contents 1.0introduction ................................ ................................ ................................ ... 4 1.1general descri ption ................................ ................................ ............. 4 1.2ax84110 block diagram ................................ ................................ ..... 4 1.3ax84110 p in connection diagram ................................ ...................... 5 2.0 signal description ................................ ................................ ...................... 10 3.0 eeprom memory mapping ................................ ................................ ...... 13 4.0 usb commands ................................ ................................ ......................... 14 4.1 usb standard commands ................................ ................................ . 14 4.2 usb vendor commands ................................ ................................ .... 15 4.3 usb vendor and normal commands format ................................ ... 17 5.0 usb configuration structure ................................ ................................ ...... 18 5.1 usb configuration ................................ ................................ ............ 18 5.2 usb interface ................................ ................................ .................... 18 5.3 usb endpoints ................................ ................................ .................. 18 6.0 basic operation ................................ ................................ .......................... 19 6.1 process flow ................................ ................................ ...................... 19 6.2 packet format character ................................ ................................ . 21 7.0 cpu & device access functions ................................ ................................ 27 7.1 pcmcia bus type access functions ................................ .................. 27 7.2 isa bus type access functions ................................ ........................... 28 7.3 80186 cpu bus t ype access functions ................................ ............... 29 7.4 68000 cpu bus type access functions ................................ ............... 30 7.5 8051 cpu bus type access functions ................................ ................. 31 8.0 electrical specification and timing ................................ ............................ 32 8.1 absolute maximum ratings ................................ ............................. 32 8.2 general operat ion conditions ................................ ......................... 32 8.3 d.c. characteristics ................................ ................................ .......... 32 8.4 a.c. timing characteristics ................................ ............................. 33 9.0 package information ................................ ................................ ................... 47 10.0 reference design (pcmcia to usb) ................................ ........................ 49 4 ax84110 l asix electronics corp preliminary 1.0introduction 1.1general descri ption the ax84110 usb2.0 to local cpu bus controller is a high performance and with embedded 2k*16 sram. the ax84110 supported full/high speed usb device with bus power capability and supports both 8 bit and 16bit local cpu interface include mcs - 51 serie s,80186 series,mc68k series cpu and isa bus and pcmcia bus. the chip also support up to 4 additional general purpose in/out pins and receive 4 set of status change from application device. ax84110 use 128 - pin lqfp low profile package, 12mhz operation for u sb and cmos process with pure 3.3v operation with 5v i/o tolerance. 1.2ax84110 block diagram 8 bit or 16 bit local cpu interface bus general i/o eecs eeck eedi eedo dm/dp fig - 1 ax84110 block diagram usb core and inter face seeprom loader i/f usb to local cpu bus bridge gpio 2k*16 sram and memory arbiter 5 ax84110 l asix electronics corp preliminary 1.3ax84110 p in connection diagram 1.3.1 ax84110 pin connection diagram for pcmcia mode nc vss eeck eedo nc sd[7] eedi sd[1] sd[10] sd[11] sd[6] nc nc sd[12] sd[3] 128 sd[0] nc vss vdd sd[8] vdd 19 78 5 18 126 38 89 22 107 65 82 23 10 68 45 13 20 60 sa[0] 103 sa[8] 3 15 sd[15] sa[4] vdd vdd 32 sa[13] sa[7] stschg3 stschg2 8 sa[15] sa[3] sa[11] sa[5] 88 100 wait 55 48 sd[13] reg# stschg1 sa[14] sa[1] sa[10] vss sa[2] resetp sd[14] stschg4 nc 17 vdd sa[6] vss vdd 91 vss 117 72 sa[9] 59 led vdd vdd vss pvdd gpio3 gpio0 pvss pvss iois16# nc ana_xiq vss pvdd vdd gpio1 reset 64 14 21 83 58 25 2 66 43 123 94 27 74 112 40 12 127 102 124 108 46 86 109 36 111 4 56 26 16 69 54 49 114 98 79 90 53 30 75 115 118 47 7 9 95 37 28 67 92 105 101 104 119 29 62 34 71 125 24 11 63 51 97 87 116 76 gpio2 42 122 110 clki 50 testmode 39 44 85 31 41 57 52 93 121 35 106 6 81 33 99 96 73 77 1 80 84 113 120 70 61 sa[12] ireq we# iowr# oe# iord# vdd xout12m vss ce2# ce1# vdd ax84110 (for pcmcia bus i/f) vdd dp forcefs r1 dm nc nc vss nc vbus avdd nc test1 nc vss nc avss nc nc avss vc nc nc vdd test0 eecs avdd nc avss nc avss nc eptest xin12m vdd nc sd[5] sd[4] sd[2] sd[9] nc fig - 2 ax84110 pin connection diagram for pcmcia bus mode * pin 12 is extwakeup 6 ax84110 l asix electronics corp preliminary 1.3.2 ax84110 pin connection diagram for isa mode vss nc eeck nc eedo eedi sd[7] sd[1] sd[11] sd[10] sd[6] nc nc 128 sd[3] sd[12] sd[0] vdd vss nc vdd sd[8] 19 78 18 5 126 89 38 22 65 107 82 10 23 45 68 13 20 60 103 sa[0] 15 3 sa[8] sd[15] sa[4] 32 vdd vdd sa[13] sa[7] stschg3 8 stschg2 sa[15] sa[11] sa[3] 100 88 sa[5] 48 55 rdy cs# sd[13] stschg1 sa[14] sa[10] sa[1] sa[2] vss resetp stschg4 sd[14] 17 aen sa[6] vdd 91 vdd vss 72 117 vss sa[9] 59 led vdd vdd pvdd vss gpio0 gpio3 pvss pvss ana_xiq nc iois16# vss vdd pvdd gpio1 64 reset 14 83 21 58 25 2 43 66 123 94 27 74 112 40 12 127 102 124 108 46 86 36 109 111 56 4 16 26 69 49 54 98 114 79 90 30 53 75 115 118 47 7 95 9 37 28 92 67 105 101 104 29 119 34 62 125 71 11 24 97 51 63 87 116 76 42 gpio2 122 110 50 clki 39 testmode 85 44 31 57 41 93 52 121 35 106 81 6 33 99 96 73 1 77 84 80 113 120 61 70 sa[12] ireq memw# iowr# memr# iord# vdd xout12m vss nc bhe# vdd ax84110 (for isa bus i/f) vdd dp forcefs r1 dm nc nc vss vbus nc nc avdd test1 nc vss nc avss nc nc avss vc nc nc vdd test0 eecs nc avdd avss nc nc avss eptest xin12m vdd nc sd[5] sd[9] sd[2] sd[4] nc fig - 3 ax84110 pin connection diagram for isa bus m ode * pin 12 is extwakeup 7 ax84110 l asix electronics corp preliminary 1.3.3 ax84110 pin connection diagram for 80x86 mode nc vss eedo nc eeck sd[1] sd[7] eedi sd[10] sd[11] nc nc sd[6] sd[12] sd[3] 128 sd[0] nc vss vdd sd[8] vdd 19 78 18 126 5 38 89 22 65 107 10 82 45 23 13 68 60 20 103 15 sa[0] 3 sa[8] sa[4] sd[15] vdd 32 vdd sa[13] sa[7] stschg3 8 stschg2 sa[15] sa[11] 100 sa[3] 88 55 48 sa[5] rdy sd[13] cs# stschg1 sa[14] sa[1] sa[10] vss sa[2] resetp stschg4 17 sd[14] nc sa[6] vdd 91 vss vdd 117 72 vss sa[9] 59 led vdd vdd pvdd vss gpio3 gpio0 pvss pvss nc ana_xiq nc vss vdd pvdd gpio1 reset 64 14 21 83 58 25 2 66 43 123 94 74 27 112 40 12 127 102 124 108 46 86 111 109 36 4 56 26 16 69 49 54 98 79 114 90 53 30 75 115 118 7 47 9 95 28 37 92 67 105 101 104 119 29 62 34 125 71 11 24 51 97 63 87 116 76 gpio2 42 122 110 50 testmode 39 clki 44 85 31 57 41 93 121 52 35 106 81 6 33 99 96 73 1 77 84 113 80 61 120 70 sa[12] ireq iowr# memw# memr# xout12m vdd iord# vss bhe# nc (for x86 interface) ax84110 vdd vdd forcefs dp dm r1 nc vss nc vbus nc nc test1 avdd nc nc vss avss nc nc vc avss nc nc vdd eecs test0 avdd nc nc avss avss nc xin12m eptest vdd nc sd[2] sd[9] sd[5] nc sd[4] fig - 4 ax84110 pin connection diagram for 80x86 mode * pin 12 is extwakeup 8 ax84110 l asix electronics corp preliminary 1.3.4 ax84110 pin connection diagram for mc68k mode 101 104 119 29 62 34 125 71 11 24 51 97 63 87 116 76 gpio2 42 122 110 50 testmode 39 clki 44 85 31 57 41 93 121 52 35 106 81 6 33 99 96 73 1 77 84 113 80 61 120 70 sa[12] ireq r/w# nc nc xout12m vdd nc vss uds# nc (for 68k interface) ax84110 vdd vdd forcefs dp dm r1 nc vss nc vbus nc nc test1 avdd nc nc vss avss nc nc vc avss nc nc vdd eecs test0 avdd nc nc avss avss nc xin12m eptest nc vdd sd[2] sd[9] sd[5] nc sd[4] nc vss eedo nc eeck sd[1] sd[7] eedi sd[10] sd[11] nc nc sd[6] sd[12] sd[3] 128 sd[0] nc vss vdd sd[8] vdd 19 78 18 126 5 38 89 22 65 107 10 82 45 23 13 68 60 20 103 15 lds# 3 sa[8] sa[4] sd[15] vdd 32 vdd sa[13] sa[7] stschg3 8 stschg2 sa[15] sa[11] 100 sa[3] 88 55 48 sa[5] dtack# sd[13] cs# stschg1 sa[14] sa[1] sa[10] vss sa[2] resetp stschg4 17 sd[14] nc sa[6] vdd 91 vss vdd 117 72 vss sa[9] 59 led vdd vdd pvdd vss gpio3 gpio0 pvss pvss nc ana_xiq nc vss vdd pvdd gpio1 reset 64 14 21 83 58 25 2 66 43 123 94 74 27 112 40 12 127 102 124 108 46 86 111 109 36 4 56 26 16 69 49 54 98 79 114 90 53 30 75 115 118 7 47 9 95 28 37 92 67 105 fig - 5 ax84110 pin connection diagram for mc68k mode * pin 12 is extwakeup 9 ax84110 l asix electronics corp preliminary 1.3.5 ax841 10 pin connection diagram for mcs - 51 mode 111 109 36 4 56 26 16 69 49 54 98 79 114 90 53 30 75 115 118 7 47 9 95 28 37 92 67 105 101 104 119 29 34 62 125 71 24 11 97 63 51 87 116 76 42 gpio2 122 110 39 clki 50 testmode 44 85 31 41 57 121 52 93 35 106 81 6 33 96 99 73 77 1 84 113 80 120 70 61 ireq sa[12] memw# memr# iowr# vdd iord# vss xout12m nc ax84110 vdd nc vdd (for 8051 interface) dp r1 forcefs nc dm nc vbus vss nc avdd nc nc test1 vss avss nc nc avss nc nc vc vdd nc eecs test0 nc avdd avss nc nc avss eptest vdd xin12m sd[9] sd[5] nc nc sd[4] sd[2] nc vss eedo nc eeck sd[1] sd[7] eedi sd[10] sd[11] nc nc sd[6] sd[12] sd[3] 128 sd[0] nc vss vdd sd[8] vdd 19 78 18 126 5 38 89 22 65 107 10 82 45 23 13 68 60 20 103 15 sa[0] 3 sa[8] sa[4] sd[15] vdd 32 vdd sa[13] sa[7] stschg3 8 stschg2 sa[15] sa[11] 100 sa[3] 88 55 48 sa[5] rdy sd[13] cs# stschg1 sa[14] sa[1] sa[10] vss sa[2] resetp stschg4 17 sd[14] psen# sa[6] vdd 91 vss vdd 117 72 vss sa[9] 59 led vdd vdd pvdd vss gpio3 gpio0 pvss pvss nc ana_xiq nc vss vdd pvdd gpio1 reset 64 14 21 83 58 25 2 66 43 123 94 74 27 112 40 12 127 102 124 108 46 86 fig - 6 ax84110 pin connection diagram for mcs - 51 mode * pin 12 is extwakeup 10 ax84110 l asix electronics corp preliminary 2.0 signal description the following terms describe the ax84110 pin - out: all pin names with the ?#? suffix are asserted low. the following abbreviati ons are used in following tables. i input pu internal pull up (100k) o output pd internal pull down (100k) i/o input/output p power pin od open drain f failsafe signal type pin no. description nc 1 no connec tion nc 2 no connection r1 i 3 constant - voltage pin a 6.2k ? 1% resistors is connected to avss. be sure to make the line between r1 and each resistor as short as possible. avdd p 4 power supply pin for analog circuits +3.3v dc avss p 5 power supply pin for analog circuits ground avss p 6 power supply pin for analog circuits ground dp b 7 usb data line data+ avss p 8 power supply pin for analog circuits ground dm b 9 usb data line data - avss p 10 power supply pin for analog circuits ground avdd p 11 power supply pin for analog circuits +3.3v dc extwakeup i/pd 12 remote - wakeup trigger from external pin. it active high and should be keep high over 2 clocks (12mhz). vbus i/pd 13 usb cable power supply pin nc i/pd 14 for testing vdd p 15 power supply pin for logic circuits +3.3v dc nc o 16 for testing nc o 17 for testing forcefs i/pd 18 when the pin is set, it must be force to work on full speed mode. nc i/pd 19 for testing vss p 20 power supply +0v dc or ground power test1 i/pu 21 test pin: thi s pin for test purpose only pull up the pin or keep no connection for normal operation test0 i/pu 22 test pin: this pin for test purpose only pull up the pin or keep no connection for normal operation vdd p 23 power supply pin for logic circuits +3.3v dc nc o 24 for testing nc o 25 for testing nc o 26 for testing nc o 27 for testing nc o 28 for testing nc o 29 for testing nc o 30 for testing nc o 31 for testing vss p 32 power supply +0v dc or ground power vdd p 33 power supply pin for logic circ uits +3.3v dc eecs o 34 eeprom chip select signal 11 ax84110 l asix electronics corp preliminary eeck o 35 eeprom clock connected to eeprom clock pin eedi o 36 eeprom data in :signal connected eeprom data input pin eedo i/pd 37 eeprom data out :signal connected eeprom data output pin nc i/pd 38 fo r testing nc i/pd 39 for testing nc i/pd 40 for testing nc i/pd 41 for testing nc i/pd 42 for testing nc i/pd 43 for testing vdd p 44 power supply pin for logic circuits +3.3v dc vss p 45 power supply +0v dc or ground power sd[15:0] i/o/f 63 - 56 53 - 46 system data bus: signal sd[15:0] constitute the bi - directional data bus. vdd p 54 power supply pin for logic circuits +3.3v dc vss p 55 power supply +0v dc or ground power vdd p 64 power supply pin for logic circuits +3.3v dc vss p 65 power supply + 0v dc or ground power ce1# o 66 card enable: the ce1# enables even numbered address bytes ce2# or bhe# or uds# o 67 card enable: the ce2# enables odd numbered address bytes for pcmcia mode. bus high enable: bus high enable is active low signal in some 16 - bit application mode. upper data strobe: the signal also name upper data strobe (/uds) for 68k application mode. oe# or memr# o 68 output enable or memory read: the signal is low active for memory read. iord# o 69 i/o read: the signal is low active for i/o read. iowr# o 70 i/o write: the signal is low active for i/o write. we# or memw# o 71 write enable or memory write: the signal is low active for memory write. ireq or ireq# i/pu/f 72 interrupt request: ireq or ireq# user can define high or low activ e. when the ireq or ireq# is asserted to indicate the host system that the application device requires host software service. vss p 73 power supply +0v dc or ground power vdd p 74 power supply pin for logic circuits +3.3v dc sa[15:1] ,sa[0] or lds# o 75 - 82 85 - 92 system address: signal sa[15:0] io address decoding for up to 64 kbyte. sa[0] also means lower data strobe (lds#) active low signal in 68k application mode. vss p 83 power supply +0v dc or ground power vdd p 84 power supply pin for logic cir cuits +3.3v dc resetp or resetp# o 93 reset: resetp or resetp# user can define high or low active. wait or wait# or rdy or dtack# i/pu/f 94 wait: wait or wait # user can define high or low active. this signal is set active, it insert wait state states during remote dma transfer. ready: as the above same dtack#: as above same for motorola cpu, the pin is active inform that application device data is accepted. aen or psen# o 95 address enable: the signal is asserted when the address bus is available for dma cycle. psen: the signal is active low for 8051program access. vdd p 96 power supply pin for logic circuits +3.3v dc vss p 97 power supply +0v dc or ground power reg# or cs# o 98 attribute memory and i/o space select: when the reg# signal is asserte d, access is limited to attribute memory and to the i/o space (only for pcmcia mode). 12 ax84110 l asix electronics corp preliminary chip select:when the cs# is asserted, the application is selected. stschg1 i/pd 99 status change: reply application device status to host stschg2 i/pd 100 status change : reply application device status to host stschg3 i/pd 101 status change: reply application device status to host stschg4 i/pd 102 status change: reply application device status to host iois16# i/pu/f 103 i/o is 16 bit port: the iois16# is asserted and i/o port addressed is capable of 16 - bit access. vdd p 104 power supply pin for logic circuits +3.3v dc led o 105 led indicator: when link fs, drives logic high always. when link hs, the pin drives logic low and it will drives high/low a period when line has activity (data transfer). nc i/pd 106 for testing gpio[3:0] i/o/pu 110 - 107 general purpose input / output pins. vdd p 111 power supply pin for logic circuits +3.3v dc ana_xiq i 112 sets the iq mode this pin is used during testing. it must be set t o low in iq measurement mode. 0: iq mode 1: normal operation mode vdd p 113 power supply pin for logic circuits +3.3v dc clki i/pd 114 for testing testmode i/pd 115 for testing (testmode) 0: normal operation mode 1: external clock synchronization mode reset i 116 when assert, place ax84110 into reset mode immediately. reset complete loads the eeprom data. vss p 117 power supply +0v dc or ground power vss p 118 power supply +0v dc or ground power vdd p 119 power supply pin for logic circuits +3.3v dc vdd p 120 power supply pin for logic circuits +3.3v dc pvdd p 121 power supply pin for pll and oscillator circuits +3.3v dc pvdd p 122 power supply pin for pll and oscillator circuits +3.3v dc pvss p 123 power supply pin for pll and oscillator circuits +0v dc or ground power pvss p 124 power supply pin for pll and oscillator circuits +0v dc or ground power vc i 125 monitor pin for two pll charge pumps connect to gnd on pcb when actually using ptest i 126 charge pump monitor on/off: connect to gnd on pcb when actually using xin12m i 127 12m crystal oscillator input xout12m o 128 12m crystal oscillator output tab - 1 pin signals 13 ax84110 l asix electronics corp preliminary 3.0 eeprom memory mapping eeprom offset high byte low byte 00h reserved word count for preload 01h *flag 02h high - sp eed length of device descriptor(byte) high - speed eeprom of device descriptor 03h high - speed length of configuration descriptor(byte) high - speed eeprom of configuration descriptor 04h reserved reserved 05h reserved reserved 06h reserved reserved 07h la nguage id high byte language id low byte 08h length of string index 1 eeprom offset of string index 1 09h length of string index 2 eeprom offset of string index 2 0ah length of string index 3 eeprom offset of string index 3 0bh length of string index 4 eeprom offset of string index 4 0ch length of string index 5 eeprom offset of string index 5 0dh length of string index 6 eeprom offset of string index 6 0eh length of string index 7 eeprom offset of string index 7 0fh reserved reserved 10h reserved reserved 11h reserved reserved 12h reserved reserved 13h full - speed length of device descriptor(byte) full - speed eeprom of device descriptor 14h full - speed length of configuration descriptor(byte) full - speed eeprom of configuration descriptor 15h - 1fh reserved reserved tab - 2 eeprom memory mapping note: *flag: n bit0 self power (for usb getstatus) 1:self power ; 0: bus power n bit1 reserved n bit2 remote wakeup support n bit3 1 n bit4 - 6 reserved n bit7 force full speed enable ; 1:force full speed 0:not enable n bit8 set reset active value ; 1:reset active high ; 0: reset active low n bit9 - f reserved 14 ax84110 l asix electronics corp preliminary 4.0 usb commands there are three command groups for endpoint0 in ax84110 l the usb standard commands l usb communication class commands l usb vendor command s 4.1 usb standard commands l the language id is 0x0904 for english l ppll means buffer length l cc means configuration number l i i means interface number setup command data in/out description 80 06 00 01 00 00 ll pp data ppll bytes get device descriptor 80 06 00 02 00 00 ll pp data ppll bytes get configuration descriptor 80 06 00 03 00 00 ll pp data 2 bytes get supported language id 80 06 00 03 09 04 ll pp data ppll bytes get manufacture string 80 06 00 03 09 04 ll pp data ppll bytes get product string 8 0 06 00 03 09 04 ll pp data ppll bytes get serial number string 80 06 00 03 09 04 ll pp data ppll bytes get configuration string 80 06 00 03 09 04 ll pp data ppll bytes get interface 0 string 80 06 00 03 09 04 ll pp data ppll bytes get interface 1/0 str ing 80 06 00 03 09 04 ll pp data ppll bytes get interface 1/1 string 80 08 00 00 00 00 01 00 data 1 bytes get configuration 00 09 cc 00 00 00 00 00 no data set configuration 81 0a 00 00 i i 00 01 00 data 1 byte get interface 01 0b as 00 00 00 00 00 no data set interface tab - 3 usb standard commands 15 ax84110 l asix electronics corp preliminary 4.2 usb vendor commands setup command data in/out descriptor 40 80 0x 00 rr rr 00 00 no data set interface register (1) 40 81 0x 00 rr rr 00 00 no data set interface register (2) 40 82 0x 00 r r rr 00 00 no data set interface register (3) 40 83 0x 00 rr rr 00 00 no data set interface register (4) 40 84 io i i 00 00 00 00 no data set io data port for out/in 40 85 gp 00 00 00 00 00 no data set write gpios(***) 40 86 bc bc 00 00 00 00 no data s et byte count 40 87 tc 00 00 00 00 00 no data set data access timing cycle 40 89 0z 00 aa aa 00 00 no data set io or memory address function mode c0 8a 00 00 00 00 01 00 data 1 bytes set read gpios(***) c0 8b dr 00 00 00 02 00 data 2 bytes read srom 4 0 8c dr 00 mm ss 00 00 no data write srom 40 8d 00 00 00 00 00 00 no data write srom enable 40 8e 00 00 00 00 00 00 no data write srom disable 40 8f yy 00 00 00 00 00 no data set other vaule tab - 4 usb vendor commands 16 ax84110 l asix electronics corp preliminary x: n bit0 1: service vaild ; 0: no service n bit1 1: byte valid ; 0: word valid n bit2 1: memory area ; 0: i/o area n bit3 reserved y: n bit0 1: set eeprom reload trigger n bit1 1: wait high active; 0: low active n bit2 1: ireq high active; 0: low active n bit3 1: set reset (default value com from eeprom autoload) n bit7 bit6 bit5 bit4 x 0 0 0 pcmcia bus mode x 1 0 0 isa bus mode t 0 0 1 80186 cpu mode t 0 1 0 68000 cpu mode t 0 1 1 8051cpu mode t: 1: byte mode transmit/receive (only for cpu mode) x: don?t care 0: word mode transmit/receive (only for cpu mode) z: bit3 bit2 bit1 bit0 x f 0 0 for i/o device x m 0 1 attribute memory x m 1 0 common memory f: 1 support fixed port 0: not support x: don?t care when work on memory (only for pcmcia or isa bus mode), user can define byte /word mode transmitting or receiving via set this bit. m:1 byte mode 0:word mode. in cpu mode (as x86 or 68k or 51) must be set on xx01 (attribute memory) as work on memory mode and this m will be don?t care because set t. rr int register offset address (user can set the address a nd it is absolute address) i i set io data port in address (user can set i/o device data port by receiving) io set io data port out address (user can set i/o device data port by transmitting) bc set byte count (user can set byte count of byte number fo r receiving) tc set access timing cycle (min 3) (user can set read/write signal active timing of period) aa set io base or memory ( absolute address) *** read / write gpio bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 read gpi3 x gpi2 x gpi1 x gpi0 x write gpo3 gpo3en gpo2 gpo2en gpo1 gpo1en gpo0 gpo0en 17 ax84110 l asix electronics corp preliminary 4.3 usb vendor and normal commands format setup command data in/out description application device internal register normal command & usb vendor command register c0 ad1 dr 00 00 00 02 00 data 2 bytes usb vendor command read ref tab - 4 read srom 40 ad1 dr 00 mm ss 00 00 no data usb vendor command write ref tab - 4 write srom c0 ad1 ad2 ad3 ad4 ad5 wlength no data nor mal command read 40 ad1 dl1 dh1 00 00 wlength variable normal command write tab - 5 vendor and normal commands format notes: wlength must be even numbers u 40 : write command (4,8,c,10?..) for write command u c0: read command (0,2,4,6,8 ?..) for read command ad1 bit7 = 1 vendor command 0 normal command ad1 or ad2 or ad3 or ad4 or ad5 or adl bit6 = 1 d(data) only low byte valid 0 d(data) low byte & high byte valid for normal command write: ( low byte) (high byte) ex: wlength = 0c 00 variable : data out 12 bytes 0c 00 = 12 bytes address data adl 00h dl dh adl 00h dl dh adl 00h dl dh this space must fix fill with (00h) l: low byte h: high byte note: if wlength = 00 00 , it indicate no need other data out . for normal command read: if user want to read 3 set application device internal register, you can set this command a s below: c0 ad1ad2 ad3 ad4 ad5 wlength c0 02 04 06 x x 06 00 x : don?t care 3x2 = 6 bytes 18 ax84110 l asix electronics corp preliminary 5.0 usb configuration structure 5.1 usb configuration the ax84110 supports 1 configuration only. 5.2 usb interface the ax8411 0 supports 2 interfaces, the interface 0 is data interface and interface 1 for communication interface. 5.3 usb endpoints the ax84110 supports 4 endpoints. endpoint0 control endpoint, it is for configuration device. endpoint1 interrupt endpoint , it i s for reporting application device status. endpoint2 bulk out endpoint, it is for transmitting application device packet. buffer is 2k size and have 4 page. each page have 512byte space. endpoint3 bulk in endpoint, it is for receiving application dev ice packet. buffer is 1k size and have 2 page. each page have 512 byte space. 19 ax84110 l asix electronics corp preliminary 6.0 basic operation 6.1 process flow if need variable vendor command no need fig - 7 basic process flow 1. standard command (get usb standard command as get device descriptor) ex: (ref tab - 3) 80 06 00 01 00 00 ll pp get device descriptor 2. vendor command (set ax84110 command) l fixed of vendor command l variable of vendor command fixed of vendor command (for initial setup) ex: (ref tab - 4) 1.40 (80~83) 0x 00 rr rr 00 00 set interrupt register4~1 (optional by application) ax84110 provide 4 set of register about application device for interrupt status reply. 2.40 84 io i i 00 00 00 00 set i/o data port (io:out ;i i :in) 3.40 87 tc 00 00 00 00 00 set data access timing cycle data access timing cycle = control signal read/write active of period 4. 40 8f yy 00 00 00 00 00 set other value ax84110 provide variabl e parameter for variable application device. it can define some value high or low active and work on selectable mode. variable of vendor command (depend on application device) initial usb device attach states standard command vendor command 1. fixed 2. variable normal command (for device) 20 ax84110 l asix electronics corp preliminary ex: (ref tab - 4) 1.40 85 gp 00 00 00 00 00 set write gpios 2. c0 8a 00 00 00 00 01 00 set read gpios ax84110 provide optional 4 set general purpose pin (in/out) for application device. 3. 40 87 tc 00 00 00 00 00 set byte count if want to receive data from application device, it can set this command. when the command is set , ax84110 will move byte count number from application device. 4. 40 89 0z 00 aa aa 00 00 set i/o or memory address function mode ax84110 provide selectable work mode on i/o or memory (attribute & common only for pcmcia bus mode). you can set address b y this command . 5. c0 8b dr 00 00 00 02 00 set read srom 6. 40 8c dr 00 mm ss 00 00 set write srom 7. 40 8d 00 00 00 00 00 00 set srom enable 8. 40 8e 00 00 00 00 00 00 set srom disable above 4 command about srom for needed. (ref tab - 2) ax84 110 provide additional space to store some special value. you can write or read dr (eeprom offset of address) by used the command. 3. normal command (base on application device) (ref tab - 5) 21 ax84110 l asix electronics corp preliminary 6.2 packet format character the ax84110 suppor ts 4 endpoints. l control endpoint l int endpoint l bulk out endpoint l bulk in endpoint 6.2.1 control endpoint it is for configuration device. f fig - 7 control seup transaction fig - 8 control read and write sequences exa mple1: i/o single write (ref tab - 5 ) 1. host send setup token 22 ax84110 l asix electronics corp preliminary 2. host send data frame ( 40 30 55 aa 00 00 00 00) 3.when the command decode by ax84110 and send appropriate packet to application device. if finish, ax84110 will reply a ack to host. 4. ho st send in token. 5. ax84110 will send (zero length status stage) to host. 6. host reply a ack. and no - data control write is end. address[15:0] 30 data[15:0] aa55 wait# iowr# example2: i/o con tinue write (ref tab - 5 ) 1. host send setup token 2. host send data frame ( 40 30 55 aa 00 00 08 00) 3.when the command decode by ax84110 and send appropriate packet to application device. if finish, ax84110 will reply a ack to host. 4. host send out token 5. host send data frame ( 32 00 bb aa 34 00 dd cc) 6. repeat 3 . 7. host send in token 8. ax84110 will send (zero length status stage) to host. 9. host reply a ack. and control write is end. address[15:0] 30 32 34 data[15:0] aa55 aabb ddcc wait# iowr# example2: i/o continue read (ref tab - 5 ) 1. host send setup token 2. host send data frame ( c0 30 32 34 00 00 06 00) 3.when the command decode by ax84110 and s end appropriate packet to application device. if finish, ax84110 will reply a ack to host. 4. host send in token 5. ax84110 receive data frame ( aa bb cc dd ee ff) from application device and will send to host. 6. host receive data frame and r eply a ack. 7. host send out token 8. host send zero length data frame.(status stage) 9. ax84110 reply a ack. and control read is end. setup token data0 40 30 55 aa 00 00 00 00 ack handshake in token ack setup token data0 40 30 55 aa 00 00 00 00 out token ack data1 32 00 bb aa 34 00 cc dd ack in token ack data1 zero data1 zero 23 ax84110 l asix electronics corp preliminary address[15:0] 30 32 34 data[15:0] bbaa ddcc ffee wait# iord# 6.2.2 int endpoint setup token data0 c0 30 32 34 00 00 06 00 ack in data1 aa bb cc dd ee ff ack out data1 zero ack 24 ax84110 l asix electronics corp preliminary it is for reporting application device status fig - 9 interrupt transaction format example1: interrupt and status report 1. host send vendor command (re f tab - 4) set interrupt register4~1 (optional by application) 2. host will send int in token in a fixed time. 3. if no interrupt occur, ax84110 will reply a nak , otherwise ax84110 will receive data base on set interrupt register4~1 & status4~1(reply from applica tion device) and wait host send next in token. if application reply status (0110 = 6) 4. when in token occur and have int occur , ax84110 will send data frame to host. 5. host reply a ack. and int transaction is end. address[15:0] 00 02 04 data[15:0] a55a b44b c33c wait# iord# int 6.2.3 bulk out endpoint it is for transmitting application device packet. in token data0 / data1 ack in token data 5a a5 4b b4 3c c3 06 nak in token ack 25 ax84110 l asix electronics corp preliminary fig - 10 bulk transaction format example1: i/o bulk out transmit packet 1. host send vendor command (ref tab - 4) set io data port address. 2. host send out token.(if ax84110 buffer is full, it will reply a nak to host) 3. host send data frame(aa bb cc dd ???..) . pid (data 0) 4. when the command decode by ax84110 and send appropriate packet (aa bb cc dd ?.) to application device. 5. ax84110 reply a ack. and bulk out transaction is end. 6. host send out token. ax84110 buffer is full, it reply a nak to host. 7. host send out token. (when buffer is not full) 8. host send data frame (12 23 34 56 ???..). pid (data 1) 9. when the command decode by ax84110 and send appropriate packet ( 12 23 34 56 ?.) to application device. 10. ax84110 reply a ack. and bulk out tr ansaction is end. address[15:0] 10 10 data[15:0] bbaa 23 12 wait# iowr# buffer full 6.2.4 bulk in endpoint it is for receiving application device packet. out token data0 ack out token data1 ack in token data0 data1 ack in token ack out token data 0 aa bb cc dd? ack out token data 1 12 23 34 45 56 78 ack out token nak 26 ax84110 l asix electronics corp preliminary example1: i/o bulk in transmit packet 1. host send vendor command (ref tab - 4) set io data port address. 2. host send vendor command (ref tab - 4) set byte count 3.when the set byte count is set, ax84110 will mo ve data from application device. 4.host send in token, but buffer is not ready (buffer is empty) and ax84110 will reply nak. 5.when buffer is ready and in token coming, ax84110 will send data to host. it base on full/high speed (max 64 / 512 byte ). if the set byte count more than max packet, it will divide a packet into 64 byte or 512 byte. pid (data 0) 6. host reply a ack. and bulk in transaction is end. 7. host send in token, but buffer is not ready (buffer is empty) and ax84110 will rep ly nak. 8. when buffer is ready and in token coming, ax84110 will send data to host. it base on full/high speed (max 64 / 512 byte). if the set byte count more than max packet, it will divide a packet into 64 byte or 512 byte. pid (data 1) 9. host rep ly a ack. and bulk in transaction is end. address[15:0] 10 10 10 10 data[15:0] bb aa dd cc 23 12 45 34 w ait# iord# buffer empty in token nak in token data 0 aa bb cc dd? ack in token data 1 12 23 34 45 56? ack 27 ax84110 l asix electronics corp preliminary 7.0 cpu & device access functions 7.1 pcmcia bus type access functions 7.1.1 attribute memory access function attribute memory read function function mode reg# ce2# ce1# sa0 oe# we# sd[15:8] sd[7:0] standby mode x h h x x x high - z high - z byte access (8 bits) l h l l l h high - z even - byte word access (16 bits) l l l x l h not valid even - byte attribute memory write function function mode reg# ce2# ce1# sa0 oe# we# sd[ 15:8] sd[7:0] standby mode x h h x x x x x byte access (8 bits) l h l l h l x even - byte word access (16 bits) l l l x h l x even - byte 7.1.2 common memory access function common memory read function function mode reg# ce2# ce1# sa0 oe# we# sd[15:8] s d[7:0] standby mode x h h x x x high - z high - z byte access (8 bits) h h h h l l l h l l h h high - z high - z even - byte odd - byte word access (16 bits) h l l x l h odd - byte even - byte common memory write function function mode reg# ce2# ce1# sa0 oe# we# sd[ 15:8] sd[7:0] standby mode x h h x x x x x byte access (8 bits) h h h h l l l h h h l l x x even - byte odd - byte word access (16 bits) h l l x h l odd - byte even - byte 7.1.3 i/o access function i/o read function function mode reg# ce2# ce1# sa0 iord# iow r# sd[15:8] sd[7:0] standby mode x h h x x x high - z high - z byte access (8 bits) l l h h l l l h l l h h high - z high - z even - byte odd - byte word access (16 bits) l l l l l h odd - byte even - byte i/o write function function mode reg# ce2# ce1# sa0 iord# io wr# sd[15:8] sd[7:0] standby mode x h h x x x x x byte access (8 bits) l l h h l l l h h h l l x x even - byte odd - byte word access (16 bits) l l l l h l odd - byte even - byte 28 ax84110 l asix electronics corp preliminary 7.2 isa bus type access functions 7.2.1 memory access function isa bus memory read function function mode cs# bhe# sa0 memr# memw # sd[15:8] sd[7:0] standby mode x h x x x high - z high - z byte access (8 bits) l l h h l h l l h h not valid not valid even - byte odd - byte word access (16 bits) l l l l h odd - byte even - byte isa bus mem ory write function function mode cs# bhe# sa0 memr# memw # sd[15:8] sd[7:0] standby mode x h x x x x x byte access (8 bits) l l h h l h h h l l x x even - byte odd - byte word access (16 bits) l l l h l odd - byte even - byte 7.2.2 i/o access function isa bu s i/o read function function mode cs# bhe# sa0 iord# iowr# sd[15:8] sd[7:0] standby mode x h x x x high - z high - z byte access (8 bits) l l h h l h l l h h not valid not valid even - byte odd - byte word access (16 bits) l l l l h odd - byte even - byte isa bu s i/o write function function mode cs# bhe# sa0 iord# iowr# sd[15:8] sd[7:0] standby mode x h x x x x x byte access (8 bits) l l h h l h h h l l x x even - byte odd - byte word access (16 bits) l l l h l odd - byte even - byte 29 ax84110 l asix electronics corp preliminary 7.3 80186 cpu bus t ype access functions 7.3.1 memory access function 80186 cpu bus memory read function function mode cs# bhe# sa0 memr# memw # sd[15:8] sd[7:0] standby mode x h x x x high - z high - z byte access (8 bits) l l h l l h l l h h not valid odd - byte even - byte not valid word access (16 bits) l l l l h odd - byte even - byte 80186 cpu bus memory write function function mode cs# bhe# sa0 memr# memw # sd[15:8] sd[7:0] standby mode x h x x x x x byte access (8 bits) l l h l l h h h l l x odd - byte even - byte x word ac cess (16 bits) l l l h l odd - byte even - byte 7.3.2 i/o access function 80186 cpu bus i/o read function function mode cs# bhe# sa0 iord# iowr# sd[15:8] sd[7:0] standby mode x h x x x high - z high - z byte access (8 bits) l l h l l h l l h h not valid odd - b yte even - byte not valid word access (16 bits) l l l l h odd - byte even - byte 80186 cpu bus i/o write function function mode cs# bhe# sa0 iord# iowr# sd[15:8] sd[7:0] standby mode x h x x x x x byte access (8 bits) l l h l l h h h l l x odd - byte even - by te odd - byte word access (16 bits) l l l h l odd - byte even - byte 30 ax84110 l asix electronics corp preliminary 7.4 68000 cpu bus type access functions 7.4.1 68000 cpu bus access function 68000 cpu bus read function function mode cs# uds# lds# r/w# sd[15:8] sd[7:0] standby mode x h x x h igh - z high - z byte access (8 bits) l l h l l h h h not valid even - byte odd - byte not valid word access (16 bits) l l l h even - byte odd - byte 68000 cpu bus write function function mode cs# uds# lds# r/w# sd[15:8] sd[7:0] standby mode x h x x x x byte ac cess (8 bits) l l h l l h l l x even - byte odd - byte x word access (16 bits) l l l l even - byte odd - byte 31 ax84110 l asix electronics corp preliminary 7.5 8051 cpu bus type access functions 7.5.1 memory access function 8051 cpu bus memory read function function mode cs# psen sa0 memr# memw # sd[15:8] sd[7:0] standby mode x h x x x high - z high - z byte access (8 bits) l l h h l h l l h h not valid not valid even - byte odd - byte 8051 cpu bus memory write function function mode cs# psen sa0 memr# memw # sd[15:8] sd[7:0] standby mode x h x x x x x byte access (8 bits) l l h h l h h h l l x x even - byte odd - byte 7.3.2 i/o access function 8051 cpu bus i/o read function function mode cs# psen sa0 iord# iowr# sd[15:8] sd[7:0] standby mode x h x x x high - z high - z byte access (8 b its) l l h h l h l l h h not valid not valid even - byte odd - byte 8051 cpu bus i/o write function function mode cs# psen sa0 iord# iowr# sd[15:8] sd[7:0] standby mode x h x x x x x byte access (8 bits) l l h h l h h h l l x x even - byte odd - byte 32 ax84110 l asix electronics corp preliminary 8.0 electrical specification and timing 8.1 absolute maximum ratings description sym min max units operating temperature ta 0 +85 j storage temperature ts - 65 +150 j supply voltage vdd - 0.3 +3.6 v input voltage vin - 0.3 vdd+0.3 v output vol tage vout - 0.3 vdd+0.3 v lead temperature (soldering 10 seconds maximum) tl 55 +240 j note: stress above those listed under absolute maximum rating may cause permanent damage to the device. exposure to absolute maximum ratings condition for extended peri od, adversely affect device life and reliability. 8.2 general operation conditions description sym min tpy max units operating temperature ta 0 25 +70 j supply voltage vdd +3.0 +3.30 +3.6 v 8.3 d.c. characteristics (vdd = 3.0 to 3.6v , vss = 0v , t a = 0 j to 70 j ) description sym min tpy max units low input voltage vil - 0.7*vdd v high input voltage vih 0.7*vdd - v low output voltage vol - 0.4 v high output voltage voh 2.4 - v input leakage current iil - 1 +1 ua output leakage current iol - 10 +10 ua input pull - up / down resistance ri 75 k ohm description sym min tpy max units power consumption (3.3v) spt3v 150 ma 33 ax84110 l asix electronics corp preliminary 8.4 a.c. timing characteristics 8.4.1 12m_xin symbol description min typ m ax units tcyc cycle time 83.33 ns thigh clk high time 34.71 41.66 49.99 ns tlow clk low time 34.71 41.66 49.99 ns tr / tf clk skew rate 1 - 4 ns 8.4.2 reset timing symbol description min typ max units trst reset pulse width (6ms ~ 10 ms) 100 - - 12m_xin 12m_xin thigh tr tf tlo tcyc 12m_xin reset/reset 34 ax84110 l asix electronics corp preliminary 8.4.3 serial eeprom timing symbol description min typ max units tclk eeck clock cycle time 187.5 khz tch eeck clock high time 2666 ns tcl eeck clock low time 2666 ns tdv eedi data valid output to eeck high time 2666 ns tod eeck high to eedi data output delay time 2666 ns tscs eecs valid to eeck high time 2666 ns thcs eeck low to eecs invalid time 0 ns tlcs minimum eecs low time 23904 ns ts data input setup time 10 ns th data input hold time 100 ns eeck tcl tch tcl tscs tdv v alid valid data valid ts th tod thcs tlcs eedi (output) eecs eedo (input) 35 ax84110 l asix electronics corp preliminary 8.4.4 pcmcia attribute memory rea d timing symbol description min typ max units tcr read cycle time * - - ns tsu(a) address setup time 60 - - ns tsu(ce) card enable setup time (ce1) 60 - - ns tsu(ce2) card enable setup time (ce2) 30 - - ns tsu(reg) register select setup time 60 - - ns th(a) address hold time 30 - - ns th(ce) card enable hold time (ce1) 30 - - ns th(ce2) card enable hold time (ce2) 30 - - ns th(reg) regist er select hold time 30 - - ns tv(wt) wait valid from oe# - - 20 ns tw(wt) wait# pulse width 0 - - ns tdis(wt) oe# high from wait# disable 30 - - ns ten(oe) data enable time from oe# 0 - - ns tdis(oe) data disable time from oe# 30 - - ns tw(oe) oe# pu lse width ** - - ns * tcr = tsu(a) + tw(oe) + th(a) ** tw(oe) = base on tab - 4 set data access timing cycle (tc) no wait condition ( tw(wt) = 0 ) = tv(wt) + tw(wt) + tdis (wt) wait condition ( tw(wt) != 0 ) 1. no wait condition if you set tc = 06 tw(oe) = tc * 30 = 6*30 = 180ns tcr = 270 ns 2. wait condition if you set tc = 06 tv(wt) = 20ns, tw(wt) = 40ns, tdis (wt) = 30ns tw(oe) = 90ns tcr = 180 ns sa[15:0] sd[15:0] reg# ce1# ce2# oe# wait# tsu(a) tcr tdis(oe) ten(oe) th(a) th(ce) tv(wt) tw(wt) tsu(ce) data valid tsu(ce2) tw(oe) tsu(reg) tdis (wt) th(ce2) th(reg) 36 ax84110 l asix electronics corp preliminary 8.4.5 pcmcia attribute memory write timing symbol description min typ max units tcw write cycle time * - - ns tsu(a) address setup time 60 - - ns tsu(ce) card enable setup time (ce1) 60 - - ns tsu(ce2) card e nable setup time (ce2) 30 - - ns tsu(reg) register select setup time 60 - - ns th(a) address hold time 30 - - ns th(ce) card enable hold time (ce1) 30 - - ns th(ce2) card enable hold time (ce2) 30 - - ns th(reg) register select hold time 30 - - ns tv (wt) wait valid from we# - - 20 ns tw(wt) wait# pulse width 0 - - ns tdis(wt) we# high from wait# disable 30 - - ns ten(we) data enable time from we# 30 - - ns th(we) data disable time from we# 30 - - ns tw(we) we# pulse width ** - - ns * tcw = tsu(a ) + tw(we) + th(a) ** tw(we) = base on tab - 4 set data access timing cycle (tc) no wait condition ( tw(wt) = 0 ) = tv(wt) + tw(wt) + tdis (wt) wait condition ( tw(wt) != 0 ) 1. no wait condition if you set tc = 06 tw(we) = tc * 30 = 6*30 = 18 0ns tcw = 270 ns 2. wait condition if you set tc = 06 tv(wt) = 20ns, tw(wt) = 40ns, tdis (wt) = 30ns tw(we) = 90ns tcw = 180 ns sa[15:0] sd[15:0] reg# ce1# ce2# we# wait# tcw tw(we) tsu(a) tw(wt) data valid th(we) th(ce) tdis(wt) tv(wt) tsu(ce) tsu(ce2) tsu(reg) ten(we) th(a) th(reg) th(ce2) 37 ax84110 l asix electronics corp preliminary 8.4.6 pcmcia common memory read timing symbol description min typ max units tcr read cycle time * - - ns tsu(a) address setup time 60 - - ns tsu(ce) card enable setup time (ce1) 60 - - ns tsu(ce2) card enable setup time (ce2) 30 - - ns th(a) address hold time 30 - - ns th(ce) card enable hold time (ce1) 30 - - ns th(ce2) card enable hold time (ce2) 30 - - ns tv(wt) wait valid from oe# - - 20 ns tw(wt) wait# pulse width 0 - - ns tdis(wt) oe# high from wait# disable 30 - - ns ten(oe) data enable time f rom oe# 0 - - ns tdis(oe) data disable time from oe# 30 - - ns tw(oe) oe# pulse width ** - - ns * tcr = tsu(a) + tw(oe) + th(a) ** tw(oe) = base on tab - 4 set data access timing cycle (tc) no wait condition ( tw(wt) = 0 ) = tv(wt) + tw(wt) + tdis (wt) wait condition ( tw(wt) != 0 ) 1. no wait condition if you set tc = 06 tw(oe) = tc * 30 = 6*30 = 180ns tcr = 270 ns 2. wait condition if you set tc = 06 tv(wt) = 20ns, tw(wt) = 40ns, tdis (wt) = 30ns tw(oe) = 90ns tcr = 180 ns sa[15:0] sd[15:0] reg# ce1# ce2# oe# wait# tsu(a) tcr tdis(oe) ten(oe) th(a) th(ce) tv(wt) tw(wt) tsu(ce) data valid tsu(ce2) tw(oe) tdis(wt) th(ce2) 38 ax84110 l asix electronics corp preliminary 8.4.7 pcmcia common memory write timing symbol description min typ max units tcw write cycle time * - - ns tsu(a) address setup time 60 - - ns tsu(ce) card enable setup time (ce1) 60 - - ns tsu(ce2) card enable setup time (ce2) 30 - - ns th(a) address hold time 30 - - ns th(ce) card enable hold time (ce1) 30 - - ns th(ce2) card enable hold time (ce2) 30 - - ns tv(wt) wait valid from we# - - 20 ns tw(wt) wait# pulse width 0 - - ns tdis(wt) we# high from wait# disable 30 - - ns ten(we) data enable time from we# 30 - - ns th(we) data disable time from we# 30 - - ns tw(we) we# pulse width ** - - ns * tcw = tsu(a) + tw(we) + th(a) ** t w(we) = base on tab - 4 set data access timing cycle (tc) no wait condition ( tw(wt) = 0 ) = tv(wt) + tw(wt) + tdis (wt) wait condition ( tw(wt) != 0 ) 1. no wait condition if you set tc = 06 tw(we) = tc * 30 = 6*30 = 180ns tcw = 270 ns 2. wait condition if you set tc = 06 tv(wt) = 20ns, tw(wt) = 40ns, tdis (wt) = 30ns sa[15:0] sd[15:0] reg# ce1# ce2# we# wait# tcw tw(we) tsu(a) tw(wt) data valid tdis(we) th(ce) tdis(wt) tv(wt) tsu(ce) tsu(ce2) ten(we) th(a) th(ce2) 39 ax84110 l asix electronics corp preliminary tw(we) = 90ns tcw = 180 ns 8.4.8 pcmcia i/o read timing 40 ax84110 l asix electronics corp preliminary symbol description min typ max units tcr read cycle time * - - ns tsu(a) address setup time 60 - - ns tsu(ce) card enable setup time (ce1) 60 - - ns tsu(ce2) card enable setup time (ce2) 30 - - ns tsu(reg) register select setup time 60 - - ns th(a) address hold time 30 - - ns th(ce) card enable hold time (ce1) 30 - - ns th(ce2) card enable hold time (ce2) 30 - - ns th(reg) register select hold time 30 - - ns tv(wt) wait valid from i ord# - - 20 ns tw(wt) wait# pulse width 0 - - ns tdis(wt) iord# high from wait# disable 30 - - ns ten(iord) data enable time from iord# 0 - - ns tdis(iord) data disable time from iord# 30 - - ns tw(iord) iord# pulse width ** - - ns tdfiois16 iois16# delay falling from address - - 10 ns tdriois16 iois16# delay rising from address 0 - - ns * tcr = tsu(a) + tw(iord) + th(a) ** tw(iord) = base on tab - 4 set data access timing cycle (tc) no wait condition = tv(wt) + tw(wt) + tdis (wt) wait condit ion 8.4.9 pcmcia i/o write timing sa[15:0] sd[15:0] reg# ce1# ce2# iord# wait# iois16# tdis(iord) data valid tw(wt) tsu(reg) tsu(ce) tw(iord) tdfiois16 tv(wt) tdriois16 th(ce) th(reg) th(a) tcr tsu(a) tsu(ce2) ten(iord) tdis(wt) th(ce2) 41 ax84110 l asix electronics corp preliminary symbol description min typ max units tcw write cycle time * - - ns tsu(a) address s etup time 60 - - ns tsu(ce) card enable setup time (ce1) 60 - - ns tsu(ce2) card enable setup time (ce2) 30 - - ns tsu(reg) register select setup time 60 - - ns th(a) address hold time 30 - - ns th(ce) card enable hold time (ce1) 30 - - ns th(ce2) ca rd enable hold time (ce2) 30 - - ns th(reg) register select hold time 30 - - ns tv(wt) wait valid from iowr# - - 20 ns tw(wt) wait# pulse width 0 - - ns tdis(wt) iowr# high from wait# disable 30 - - ns ten(iowr) data enable time from iowr# 30 - - ns th(iowr) data disable time from iowr# 30 - - ns tw(iowr) iowr# pulse width ** - - ns tdfiois16 iois16# delay falling from address - - 10 ns tdriois16 iois16# delay rising from address 0 - - ns * tcw = tsu(a) + tw(iowr) + th(a) ** tw(iowr) = base on ta b - 4 set data access cycle (tc) no wait condition ( tw(wt) = 0 ) = tv(wt) + tw(wt) + tdis (wt) wait condition ( tw(wt) != 0 ) 8.4.9 isa bus access i/o timing sa[15:0] sd[15:0] reg# ce1# ce2# iowr# wait# iois16# ten(iowr) th(iowr) data valid tw(wt) tsu(reg) tsu(ce) tw(iowr) tsu(a) tdfiois16 tv(wt) tdriois16 th(ce) th(reg) th(a) tdis(wt) tcw tsu(ce2) th(ce2) tc 42 ax84110 l asix electronics corp preliminary symbol description min typ max units tc cycle time * - - ns tsu(a) address setup time 60 - - ns tsu(cs) chip select setup time 60 - - ns tsu(bhe) byte high enable setup time 30 - - ns t h(a) address hold time 30 - - ns th(cs) chip select hold time 30 - - ns th(bhe) byte high enable hold time 30 - - ns tv(rdy) rdy valid from io# - - 20 ns tw(rdy) rdy# pulse width 0 - - ns tdis(rdy) io# high from rdy# disable 30 - - ns ten(iord) data enable time from iord# 0 - - ns tdis(iord) data disable time from iord# 30 - - ns ten(iowr) data enable time from iowr# 30 - - ns th(iowr) data disable time from iowr# 30 - - ns tw(io) io# pulse width ** - - ns tv(cs16 - a) iois16# valid from address c hange - - 10 ns tdis(cs16 - a) iois16# disable from address change 0 - - ns * tc = tsu(a) + tw(io) + th(a) io: include (iowr & iord) ** tw(io) = base on tab - 4 set data access cycle (tc) no wait condition ( tw(rdy) = 0 ) = tv(rdy) + tw(rdy) + tdis (rdy ) wait condition (tw(rdy) != 0) sa[15:0] sd[1 5:0] aen# iowr# rdy iois16# data valid data valid iord# sd[15:0] bhe# cs# tsu(aen) tsu(a) tsu(bhe) tsu(cs) tv(cs16 - a) tv(rdy) tdis(cs16 - a) th(aen) th(a) th(cs) th(bhe) ten(iowr) ten(iord) tw(rdy) tdis(rdy) th(iowr) tdi s(iord) tw(io) 43 ax84110 l asix electronics corp preliminary 8.4.10 isa bus access mem timing tc 44 ax84110 l asix electronics corp preliminary symbol descr iption min typ max units tc cycle time * - - ns tsu(a) address setup time 60 - - ns tsu(cs) chip select setup time 60 - - ns tsu(bhe) byte high enable setup time 30 - - ns th(a) address hold time 30 - - ns th(cs) chip select hold time 30 - - ns th( bhe) byte high enable hold time 30 - - ns tv(rdy) rdy valid from mem# - - 20 ns tw(rdy) rdy# pulse width 0 - - ns tdis(rdy) mem# high from rdy# disable 30 - - ns ten(memr) data enable time from memr# 0 - - ns tdis(memr) data disable time from memr# 3 0 - - ns ten(memw) data enable time from memw # 30 - - ns th(memw) data disable time from memw # 30 - - ns tw(mem) mem # pulse width ** - - ns * tc = tsu(a) + tw(mem) + th(a) mem: include (memr & memw) ** tw(mem) = base on tab - 4 set data access cycle (tc) no wait condition ( tw(rdy) = 0 ) = tv(rdy) + tw(rdy) + tdis (rdy) wait condition (tw(rdy) != 0) 8.4.11 80186 type access timing sa[15:0] sd[15:0](write) aen memr# rdy data valid data valid memw# sd[15:0](read) bhe# cs# tsu(aen) tsu(a) tsu(bhe) tsu(cs) tv(rdy) th(aen) th(a) th(cs) th(bhe) ten(iowr) ten(iord) tw(rdy) tdis(rdy) th(iowr) tdis(io rd) tw(mem) 45 ax84110 l asix electronics corp preliminary symbol description min typ max units tc cycle time * - - ns tsu(a) address setup time 60 - - ns tsu(cs) chip select setup time 60 - - ns tsu(bhe) byte high enable setup time 30 - - ns th(a) address hold time 30 - - ns th(cs) chip select hold time 30 - - ns th(bhe) byte high enable hold time 30 - - ns tv(rdy) rdy valid from mem# - - 20 ns tdis(rdy) op# high from rdy# disable 0 - - ns ten(rd) data enable time from op# 0 - - ns tdis(rd) data disable time from op# 30 - - ns ten(wr) da ta enable time from op # 30 - - ns th(wr) data disable time from op # 30 - - ns tw(op) op # pulse width ** - - ns * tc = tsu(a) + tw(op) + th(a) op: include (memr & memw & iowr & iord) ** tw(op) = base on tab - 4 set data access cycle (tc) 8.4.12 68k ty pe access timing sa[15:0] sd[15:0](write) iowr# rdy data valid data valid iord# sd[15:0](read) bhe# cs# memr# memw# tc tsu(bhe) tv(rdy) tdis(rdy) tdis(rd) th(wr) ten(wr) ten(rd) th(bhe) tsu(cs) tsu(a) th(a) th(cs) tw(op) tc tsu(a) th(a) 46 ax84110 l asix electronics corp preliminary symbol description min typ max units tc cycle time * - - ns tsu(a) address setup time 60 - - ns tsu(cs ) chip select setup time 60 - - ns tsu(uds) upper data strobe setup time 60 - - ns tsu(lds) lower data strobe setup time 60 - - ns th(a) address hold time 30 - - ns th(cs) chip select hold time 30 - - ns th(uds) upper data strobe hold time 30 - - n s th(lds) lower data strobe hold time 30 - - ns tv(dtack) dtack valid from uds# or lds# - - 20 ns tdis(dtack) dtack disable from uds# or lds# 0 - - ns ten(rd) data enable time from uds# or lds# 0 - - ns tdis(rd) data disable time from uds# or lds# 30 - - ns ten(wr) data enable time from r/w (write) 30 - - ns th(wr) data disable time from r/w (write) 30 - - ns tw(wr) wr # pulse width ** - - ns * tc = tsu(a) + tw(wr) + th(a) ** tw(wr) = base on tab - 4 set data access cycle (tc) 8.4.12 8051 bus a ccess timing tc sa[15:1] sd[1 5:0](write) dtack# data valid data valid sd[15:0](read) uds# (read) r/w (write) r/w cs# tsu(cs) tw(wr) ten(wr) ten(rd) tv(dtack) tdis(dtack) th(cs) tdis(rd) th(wr) tsu(uds) th(uds) lds# tsu(lds) th(lds) 47 ax84110 l asix electronics corp preliminary symbol description min typ max units tc cycle time * - - ns tsu(a) address setup time 60 - - ns tsu(cs) chip select setup time 60 - - ns tsu(psen) psen setup time 60 - - ns th(a) address hold time 30 - - ns th(cs) chip select hold time 30 - - ns th(psen) psen hold time 30 - - ns tv(rdy) rdy valid from op# - - 20 ns tdis(rdy) op# high from rdy# disable 0 - - ns ten(rd) data enable time from op# 0 - - ns tdis(rd) data disable time from op# 30 - - ns ten(wr) data enable time from op # 30 - - ns th(wr) data disable time from op # 30 - - ns tw(op) op # pulse width ** - - ns * tc = tsu(a) + tw(op) + th(a) op: in clude (memr & memw & iowr & iord) ** tw(op) = base on tab - 4 set data access cycle (tc) 9.0 package information sa[15:0] cs# psen sd[15:0](write) iowr# rdy data valid data valid iord# sd[15:0](read) memr# memw# tsu(psen) tsu(a) tsu(cs) tw(op) th(a) th(cs) ten(wr) ten(rd) tv(rdy) tdis(rdy) th(wr) tdis(rd) th(psen) 48 ax84110 l asix electronics corp preliminary b e d hd e he pin 1 a2 a1 l l1 q a milimeter symbol min. nom max a1 0.05 0.1 0.15 a2 1.39 1.40 1.41 a 1.70 b 0.155 0.16 0.26 d 13.9 14.0 0 14.1 e 13.9 14.00 14.1 e 0.5 hd 15.6 16.00 16.4 he 15.6 16.00 16.4 l 0.3 0.50 0.7 l1 1.00 q 0 10 49 ax84110 usb2.0 to local bus asix electronics corp 10.0 reference design (pcmcia to usb) usb to pcmcia 1.0 ax84110 dem0 board c 1 1 wednesday, december 11, 2002 title size document number rev date: sheet of vdd5 vdd33l vdd33l vdd33l vdd33l vdd33l reset wait sd14 iord# sd15 iowr# sd13 sd12 ce2# sd11 gnd sd4 sa0 sa4 sd7 sd1 sa6 we# sa7 sa2 gnd ce1# sa3 oe# sa10 sa11 sa1 ireq# sa14 sa8 sa12 sd5 sa5 sa13 sd0 sd3 sa15 sd2 gnd sa9 sd6 iois16# gnd sd9 reg# sd8 sd10 stschg# dm dp vbus stschg# vdd5 vdd33 vcc vdd33l vdd33l vdd5 vdd33 12m_xin eedo eecs vdd33 eedi eeck vcc vcc vdd33l eeck sa0 sd5 vdd33l vbus stschg2 sd12 iowr# sa12 vdd33l ce1# sa7 gnd stschg1 vdd33l sa4 gnd sd9 gnd iord# ireq# vdd33l vdd33l reg# vdd33l sd6 sd0 sd13 sa13 vdd33l sd7 12m_xout 12m_xout iois16# ce2# gnd sa6 avdd33 gnd gnd oe# vdd33l sa5 sa10 sd3 eedi rst vdd33pll rst sd10 eecs gnd sa9 vdd33pll gnd sa1 sa8 sd1 vdd33pll stschg3 sd14 sa14 vdd33l gnd eedo reset sd4 avdd33 gnd gnd gnd sd15 sd11 we# sa11 gnd avdd33 vdd33l dp vdd33l gnd vdd33l gnd dm gnd 12m_xin stschg4 wait sa2 sa3 sd2 gnd sd8 vdd33l sa15 vdd33l c20 0.1u c21 0.1u c11 22p jp2 header 4x2 1 2 3 4 5 6 7 8 c13 0.47uf c23 0.1u y1 crystal 12.000mhz r6 1m r8 0 c17 0.1u u3 93c56 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc c25 0.1u c6 0.1u + c4 22u/16v c29 0.1u c19 0.1u c9 0.1u r7 15k c31 0.1u d3 diode c12 22p r5 6.2k 1% + c15 22u/16v c35 0.1u s2 sw pushbutton tp1 test point 1 tp2 test point 1 ax84110 asix usb 2.0 to local bus/pcmcia u1 ax84110 1 2 3 4 5 6 7 8 9 10 12 19 13 14 15 16 17 18 11 20 21 22 23 24 25 26 27 28 36 45 46 47 48 49 50 51 52 53 54 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 29 30 31 32 33 34 35 37 38 39 40 41 42 43 44 55 56 72 71 70 69 68 67 66 65 62 61 60 59 58 57 64 63 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 nc nc r1 avdd avss avss dp avss dm avss extwakeup speedup vbus nc vdd linestate1 linestate0 forcefs avdd vss test1 test0 vdd nc nc nc nc nc eedi vss sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 vdd vss vdd sa15 sa14 sa13 sa12 sa11 sa10 sa9 sa8 vss vdd sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 resetp wait aen vdd nc nc nc vss vdd eecs eeck eedo nc nc nc nc nc nc vdd vss sd8 #ireq #we #iowr #iord #oe #ce2 #ce1 vss sd14 sd13 sd12 sd11 sd10 sd9 vdd sd15 vss #reg stschg1 stschg2 stschg3 stschg4 #iois16 vdd led atpgen gpio0 gpio1 gpio2 gpio3 vdd ana_xio vdd clki testmode reset vss vss vdd vdd pvdd pvdd pvss pvss vc eptest xin12m xout12m c5 0.1u + c3 22u/16v l3 f.bead. l1 f.bead. c34 0.1u d2 diode c33 0.1u l2 f.bead. c2 0.1u jp1 header 4x2 1 2 3 4 5 6 7 8 c1 1000p c28 0.1u c7 0.01u c24 0.1u r99 4.7k + c14 22u/16v c32 0.1u 4 1 2 3 j2 usb-con 4 1 3 2 gnd vdd5 d+ d- s s c37 0.1u s1 switch c18 0.1u j3 header 3 1 2 3 c26 0.1u c30 0.1u u2 pcmcia_1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 gnd d3 d4 d5 d6 d7 ce1# a10 oe# a11 a9 a8 a13 a14 we# ireq# vcc vpp1 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 d0 d1 d2 iois16# gnd gnd cd1# d11 d12 d13 d14 d15 ce2# vs1# iord# iowr# a17 a18 a19 a20 a21 vcc vpp2 a22 a23 a24 a25 vs2# reset wait# inpack# reg# spkr# stschg# d8 d9 d10 cd2# gnd l6 f.bead. c27 0.1u j1 dc power jack 1 2 3 + c16 22u/16v c39 0.1u c10 0.1u u4 ams1117 3 2 1 vin vout adj/gnd c22 0.1u + c38 22u/16v d1 led + c8 22u/16v l4 f.bead. r1 1k l5 f.bead. c36 0.1u r3 10k usb port link/act led option dc 5.0v power 5v / 3.3v option for pcmcia asix electronics corporation. dc 5.0v ---> 3.3v usb reset 50 ax84110 usb2.0 to local bus asix electronics corp revision date comment v. 0.0 12/16/2002 initial release. 4f, no.8, hsin ann rd., sc ience - based industrial park, hsinchu, taiwan, r.o.c. 579950 fax: 886 - 3 - 5799558 email: support@asix.com.tw web: http://www.asix.com.tw |
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